This invention relates generally to processing within a computing environment, and more particularly to allocating shared resources in a computing environment.
Overall computer system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor(s), any memory cache(s), the input/output (I/O) subsystem(s), the efficiency of the memory control function(s), the main memory device(s), and the type and structure of the interconnect interface(s).
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall computer system performance and density by improving the system/subsystem design and/or structure. High-availability systems present further challenges as related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems in regard to mean-time-between-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, etc. Other frequent customer requirements further exacerbate the computer system design challenges, and include such items as ease of upgrade and reduced system environmental impact (such as space, power, and cooling).
Current microprocessors have many processors, each running many threads of execution. For example, a current microprocessor may have eight processors, each with four threads, with hypervisor software being utilized to manage the multiple virtual processors. The number of simultaneous threads being executed is predicted to increase and in the future and microprocessors will likely have dozens of threads running simultaneously.
Microprocessors have many hardware resources that are shared by the multiple virtual processors that are under the control of the hypervisors. These shared resources include physical processors, caches, interconnection networks that provide cache coherence among multiple caches, memory controllers, input/output (I/O) controllers etc. Current microprocessor hardware designs rely on the hypervisor software combined with hardware timers in each physical processor to insure that virtual processors receive a fair share of the physical hardware resources. In current designs, virtual processors rely on the hypervisor to dispatch virtual processes onto physical processors in a manner that will provide each processor a fair share of “down-stream” shared resources such as cache accesses and memory controller accesses.